1. Field of the Invention
This invention relates to a booster circuit for a semiconductor memory device such as a dynamic random access memory (DRAM).
2. Description of the Prior Art
A high-density DRAM is designed so that some kinds of signals such as a word line drive signal, etc. have a voltage level which is higher than the level of the source voltage (hereinafter, referred to as "source voltage level"), in order to improve the operating allowance and other characteristics. Such a voltage level higher than the source voltage level is generated by a booster circuit provided in the DRAM chip. FIG. 5 shows an example of a prior art booster circuit. The booster circuit of FIG. 5 is disclosed in U.S. Pat. No. 4,677,313.
The operation of the booster circuit of FIG. 5 will be described with reference to FIG. 6. During the precharge period, the precharge signal .phi..sub.p is HIGH ((a) of FIG. 6), and MOS transistors 28, 29, 30 and 36 are on, so that an output signal .phi..sub.out, nodes B and D are held at the ground level ((e) and (f) of FIG. 6). A node C is precharged to a high level (V.sub.cc), and MOS transistors 22 and 25 are off. A booster MOS capacitor 31 is precharged during the precharge period through a MOS transistor 21 which is connected to the source voltage V.sub.cc. The precharge voltage of the booster MOS capacitor 31 (i.e., the voltage level of a node A) is V.sub.cc -V.sub.th (where V.sub.th is the threshold value of the MOS transistor 21), as shown in (d) of FIG. 6.
The precharge period is followed by the active period during which the precharge signal .phi..sub.p drops to the ground level and an input signal .phi..sub.in of the source voltage level V.sub.cc is input ((b) of FIG. 6). This causes a MOS capacitor 32 to be charged through a MOS transistor 23. The delay time of a delay circuit 20 is selected so that the MOS capacitor 32 is sufficiently charged. As shown in FIG. 6, when the input signal .phi..sub.in is LOW, the output of the delay circuit 20 is HIGH, and vice versa. The potential of a node C is held at a high level (V.sub.cc) by the delay operation of the delay circuit 20 until the MOS capacitor 32 is charged to a sufficient degree, so that the levels of the output signal .phi..sub.out and node D are held at a low level. The gate of a MOS transistor 35 is boosted through a MOS capacitor 38 to a level higher than the source voltage level V.sub.cc, so that a current flows into the node A via the MOS transistor 35, thereby compensating the above-mentioned potential drop. Because of this operation, the MOS capacitor 32 is sufficiently charged. When the delay time of the delay circuit 20 has elapsed, the level of the node C drops, and the MOS capacitor 38 is discharged through the MOS transistor 37 to lower the potential of the node E, resulting in the turn off of the MOS transistor 35.
When the delay time of the delay circuit 20 has elapsed (i.e., when the MOS capacitor 32 has been sufficiently charged), the MOS transistors 24 and 26 are turned off, and the potential of the node D begins to rise up to the source voltage level V.sub.cc. In the case of no-load, therefore, the potential of the node A which is capacitively coupled to the node D is raised from V.sub.cc to 2 V.sub.cc with the increase of the potential of the node D, causing the level of the output signal .phi..sub.out to be boosted via the MOS transistor 22. The MOS capacitor 32 boosts the potential of the gate (node B) of the MOS transistor 22 to a higher level. As a result, the output signal .phi..sub.out having a level higher than the source voltage level V.sub.cc is generated. The level of the output signal .phi..sub.out reaches a value as high as 2 V.sub.cc when the load of the output signal .phi..sub.out is null. Since the above-mentioned series of operations is rapidly performed as soon as the potential of the node D begins to rise, the circuit of FIG. 5 functions as a relatively fast booster circuit.
In the circuit of FIG. 5, however, the potential of the node A is lower than the source voltage level V.sub.cc during the precharge period, and is raised to the source voltage level V.sub.cc by the MOS transistor 35 after the rising of the input signal .phi..sub.in. This causes a problem in that it requires a considerably long period of time to fully charge the MOS capacitor 31, resulting in that the total period of time required for the boost operation becomes longer.